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CDC328A - 1-Line To 6-Line Clock Driver

General Description

The CDC328A contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution.

Through the use of the polarity-control inputs (T/C), various combinations of true and complementary outputs can be obtained.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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D Low Output Skew for Clock-Distribution and Clock-Generation Applications D TTL-Compatible Inputs and Outputs D Distributes One Clock Input to Six Clock Outputs D Polarity Control Selects True or Complementary Outputs D Distributed VCC and GND Pins Reduce Switching Noise D High-Drive Outputs (− 48-mA IOH, 48-mA IOL) D State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation D Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages CDC328A 1ĆLINE TO 6ĆLINE CLOCK DRIVER WITH SELECTABLE POLARITY SCAS327B − DECEMBER 1992 − REVISED NOVEMBER 1995 D OR DB PACKAGE (TOP VIEW) GND 1 1Y2 2 2Y1 3 GND 4 2Y2 5 3Y 6 GND 7 4Y 8 16 1Y1 15 1T/C 14 VCC 13 2T/C 12 A 11 VCC 10 3T/C 9 4T/C description The CDC328A contains a clock-driver circuit that