* Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
* Operates at 3.3-V VCC
* LVTTL-Compatible Inputs and Outputs
*.

* Operates at 3.3-V VCC
* LVTTL-Compatible Inputs and Outputs
* Supports Mixed-Mode Signal Operation (5-V In.

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance state. The CDC351 operates at nomi.

CDC351

CDC318A

CDC319

CDC3207G-C

CDC3207G-C3

CDC3257G-C2

CDC328A

CDC329A

CDC337

CDC339

CDC340

CDC341

CDC391