3.3-v phase-lock-loop clock driver.
D Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
D Separate Output Enable for Each Output
.
NOT RECOMMENDED FOR NEW DESIGNS
PW PACKAGE (TOP VIEW)
AGND 1 VCC 2 1Y0 3 1Y1 4 1Y2 5 GND 6 GND 7 1Y3 8 1Y4 9 VCC 10 1G 11
FBOUT 12
24 CLK 23 AVCC 22 VCC 21 2Y0 20 2Y1 19 GND 18 GND 17 2Y2 16 2Y3 15 VCC 14 2G 13 FBIN
The CDC509 is a high-performan.
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