Datasheet4U Logo Datasheet4U.com

CDC536 - 3.3-V Phase-Lock-Loop Clock Driver

General Description

The CDC536 is a high-performance, low-skew, low-jitter clock driver.

It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal.

Key Features

  • Low-Output Skew for Clock-Distribution and Clock-Generation.

📥 Download Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CDC536 www.ti.com SCAS378G – APRIL 1994 – REVISED JULY 2004 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS FEATURES • Low-Output Skew for Clock-Distribution and Clock-Generation Applications • Operates at 3.