3.3-v phase-lock-loop clock driver.
D Operates at 3.3-V VCC D Distributes Differential LVPECL Clock
Inputs to 12 TTL-Compatible Outputs
D Two Select Inputs .
The CDC582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, CLKIN) input signals. It is specifica.
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