Datasheet Summary
D Low Output Skew for Clock-Distribution and Clock-Generation Applications
D Operates at 3.3-V VCC D Distributes One Clock Input to Twelve
Outputs
D Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double the Input Frequency
D No External RC Network Required D External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS336D
- FEBRUARY 1993
- REVISED OCTOBER 1998
D Application for Synchronous DRAM,
High-Speed Microprocessor
D TTL-patible Inputs and Outputs D Outputs Drive Parallel 50-Ω Terminated
Transmission Lines
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly...