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CDC586 Datasheet 3.3-v Phase-lock-loop Clock Driver

Manufacturer: Texas Instruments

Overview: D Low Output Skew for Clock-Distribution and Clock-Generation Applications D Operates at 3.3-V VCC D Distributes One Clock Input to Twelve Outputs D Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency D No External RC Network Required D External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input CDC586 3.

General Description

The CDC586 is a high-performance, low-skew, low-jitter clock driver.

It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal.

It is specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz W on outputs configured as half-frequency outputs.

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