D Operates at 3.3-V VCC D Distributes One Clock Input to Twelve Outputs D Two Select Inputs Configure Up to Nine Outputs.

The CDC586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with.

CDC5801A

CDC5806

CDC582

CDC509

CDC516

CDC536

CDC5D23B

CDC-Z137

CDC1104

CDC111

CDC1607F-E

CDC1631F-E

CDC203