Datasheet Summary
CDCF2510 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER
ą
SCAS628D
- APRIL 1999
- REVISED DECEMBER 2004
D Use CDCVF2510A as a Replacement for this Device
D Designed to Meet PC133 SDRAM
Registered DIMM Specification Rev. 0.9
D Spread Spectrum Clock patible D Operating Frequency 25 MHz to 140 MHz D Static Phase Error Distribution at 66 MHz to 133 MHz is ±125 ps
D Jitter (cyc- cyc) at 66 MHz to 133 MHz Is
|70| ps
D Available in Plastic 24-Pin TSSOP D Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D Distributes One Clock Input to One Bank of
10 Outputs
D Output Enable Pin to Enable/Disable All 10
Outputs
D External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the...