Datasheet Summary
.ti.
SCAS904A
- MAY 2010
- REVISED JUNE 2010
Dual 1:2 Low Additive Jitter LVDS Buffer
Check for Samples: CDCLVD2102
Features
- Dual 1:2 Differential Buffer
- Low Additive Jitter <300 fs RMS in 10-kHz to
20-MHz
- Low Within Bank Output Skew of 15 ps (Max)
- Universal Inputs Accept LVDS, LVPECL,
LVCMOS
- One Input Dedicated for Two Outputs
- Total of 4 LVDS Outputs, ANSI EIA/TIA-644A
Standard patible
- Clock Frequency up to 800 MHz
- 2.375- 2.625V Device Power Supply
- LVDS Reference Voltage, VAC_REF, Available for
Capacitive Coupled Inputs
- Industrial Temperature Range
- 40°C to 85°C
- Packaged in 3mm × 3mm 16-Pin QFN (RGT)
- ESD Protection Exceeds 3 kV HBM, 1 kV...