Datasheet4U Logo Datasheet4U.com

CDCLVD2108 - Dual 1:8 Low Additive Jitter LVDS Buffer

General Description

The CDCLVD2108 clock buffer distributes two clock inputs (IN0, IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0, OUT15).

Each buffer block consists of one input and 8 LVDS outputs.

The inputs can either be LVDS, LVPECL, or LVCMOS.

Key Features

  • 1.
  • Dual 1:8 Differential Buffer.
  • Low Additive Jitter.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CDCLD080 SURFACE MOUNT SILICON CURRENT LIMITING DIODES Central Semiconductor
CDCLD100 SURFACE MOUNT SILICON CURRENT LIMITING DIODES Central Semiconductor
CDCLD120 SURFACE MOUNT SILICON CURRENT LIMITING DIODES Central Semiconductor
CDCLD200 SURFACE MOUNT SILICON CURRENT LIMITING DIODES Central Semiconductor
CDCLD400 SURFACE MOUNT SILICON CURRENT LIMITING DIODES Central Semiconductor

Other Datasheets by Texas Instruments

Part Number Description
CDCLVD2102 Dual 1:2 Low Additive Jitter LVDS Buffer
CDCLVD2104 Dual 1:4 Low Additive Jitter LVDS Buffer
CDCLVD2106 Dual 1:6 Low Additive Jitter LVDS Buffer
CDCLVD110 PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER
CDCLVD110A PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CDCLVD2108 www.ti.com SCAS905C – OCTOBER 2010 – REVISED DECEMBER 2010 Dual 1:8 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2108 FEATURES 1 • Dual 1:8 Differential Buffer • Low Additive Jitter <300 fs RMS in 10 kHz to 20 MHz • Low Within Bank Output Skew of 50 ps (Max) • Universal Inputs Accept LVDS, LVPECL, LVCMOS • One Input Dedicated for Eight Outputs • Total of 16 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible • Clock Frequency up to 800 MHz • 2.375–2.