CDCLVD2108 Description
The CDCLVD2108 clock buffer distributes two clock inputs (IN0, IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0, OUT15). Each buffer block consists of one input and 8 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.
CDCLVD2108 Key Features
- Dual 1:8 Differential Buffer
- Low Within Bank Output Skew of 50 ps (Max)
- Universal Inputs Accept LVDS, LVPECL
- One Input Dedicated for Eight Outputs
- Total of 16 LVDS Outputs, ANSI EIA/TIA-644A
- Clock Frequency up to 800 MHz
- 2.375-2.625V Device Power Supply
- Industrial Temperature Range -40°C to 85°C
- Packaged in 7mm × 7mm 48-Pin QFN (RGZ)
- ESD Protection Exceeds 3 kV HBM, 1 kV CDM