CDCLVD2102 Description
The CDCLVD2102 clock buffer distributes two clock inputs (IN0, IN1) to a total of 4 pairs of differential LVDS clock outputs (OUT0, OUT3). Each buffer block consists of one input and 2 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.
CDCLVD2102 Key Features
- Dual 1:2 Differential Buffer
- Low Within Bank Output Skew of 15 ps (Max)
- Universal Inputs Accept LVDS, LVPECL
- One Input Dedicated for Two Outputs
- Total of 4 LVDS Outputs, ANSI EIA/TIA-644A
- Clock Frequency up to 800 MHz
- 2.375-2.625V Device Power Supply
- Industrial Temperature Range -40°C to 85°C
- Packaged in 3mm × 3mm 16-Pin QFN (RGT)
- ESD Protection Exceeds 3 kV HBM, 1 kV CDM