CDCM9102 Datasheet | Texas Instruments

Product Folder Sample & Buy Technical Documents Tools & Software Support & munity Reference Design SCAS922A - FEBRUARY 2012 - REVISED APRIL 2016 CDCM9102 Low-Noise Two-Channel 100-MHz Clock Generator 1 Features - 1 Integrated Low-Noise Clock Generator Including PLL, VCO, and Loop Filter - Two Low-Noise 100-MHz Clocks (LVPECL, LVDS, or pair of LVCMOS) - Support for HCSL Signaling Levels (AC-Coupled) - Typical Period Jitter: 21 ps pk-pk - Typical Random Jitter: 510 fs RMS - Output Type Set by Pins - Bonus Single-Ended 25-MHz Output - Integrated Crystal Oscillator Input Accepts 25-MHz Crystal - Output Enable Pin Shuts Off Device and Outputs - 5-mm × 5-mm 32-Pin VQFN Package -...