Datasheet Summary
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Features
- 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications
- Spread Spectrum Clock patible
- Operating Frequency: 10 MHz to 340 MHz
- Low Current Consumption: <115 mA
- Low Jitter (Cycle-Cycle): ±30 ps
- Low Output Skew: 25 ps
- Low Period Jitter: ±20 ps
1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B
- JUNE 2005
- REVISED JULY 2007
- Low Dynamic Phase Offset: ±15 ps
- Low Static Phase Offset: ±50 ps
- Distributes One Differential Clock Input to Ten
Differential Outputs
- 52-Ball μBGA (MicroStar™ Junior BGA,
0,65-mm pitch)
- External Feedback Pins (FBIN, FBIN) are Used to Synchronize the Outputs to the Input Clocks
- Fail-Safe...