Datasheet Details
| Part number | CDCV857A |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 829.53 KB |
| Description | 2.5-V PHASE LOCK LOOP CLOCK DRIVER |
| Datasheet | CDCV857A-etcTI.pdf |
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Overview: CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER D Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications D Spread Spectrum Clock Compatible D Operating Frequency: 60 to 180 MHz D Low Jitter (cyc–cyc): ±50 ps D Distributes One Differential Clock Input to Ten Differential Outputs SCAS667A – APRIL 2001 – REVISED AUGUST 2002 D Three-State Outputs When the Input Differential Clocks Are <20 MHz D Operates From Dual 2.
| Part number | CDCV857A |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 829.53 KB |
| Description | 2.5-V PHASE LOCK LOOP CLOCK DRIVER |
| Datasheet | CDCV857A-etcTI.pdf |
|
|
|
The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT).
The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD).
When PWRDWN is high, the outputs switch in phase and frequency with CLK.
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