Datasheet Summary
CDCV857B, CDCV857BI 2.5ĆV PHASEĆLOCK LOOP CLOCK DRIVER
D Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM Applications
D Spread Spectrum Clock patible D Operating Frequency: 60 MHz to 200 MHz D Low Jitter (cycle-cycle): ±50 ps D Low Static Phase Offset: ±50 ps D Low Jitter (Period): ±35 ps D Distributes One Differential Clock Input to
10 Differential Outputs
SCAS689
- FEBRUARY 2003
D Enters Low-Power Mode When No CLK
Input Signal Is Applied or PWRDWN Is Low
D Operates From Dual 2.5-V Supplies D Available in a 48-Pin TSSOP Package or
56-Ball MicroStar Junior BGA Package
D Consumes < 100-µA Quiescent Current D External Feedback Pins (FBIN, FBIN) Are
Used to...