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LMK5C33216 - Ultra-Low Jitter Clock Synchronizer

General Description

The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.

Key Features

  • BAW APLL with 40 fs RMS jitter at 491.52 MHz.
  • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs).
  • Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz.
  • -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20 MHz TDC rate.
  • Two differential or single-ended DPLL inputs.
  • 1 Hz to 800 MHz differential.
  • Hitless switching with phase cancellation and/or phase slew control.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.ti.com LMK5C33216 SNAS750B – NOVEMBER 2020 – REVISLEMD MKA5RCC3H32201261 SNAS750B – NOVEMBER 2020 – REVISED MARCH 2021 LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW 1 Features • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.