* BAW APLL with 40 fs RMS jitter at 491.52 MHz
* Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs)
* Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz
* -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC nois
LMK5C33216 Datasheet (4.20 MB)
LMK5C33216
4.20 MB
Ultra-low jitter clock synchronizer.
www.ti.com LMK5C33216 SNAS750B NOVEMBER 2020 REVISLEMD MKA5RCC3H32201261 SNAS750B NOVEMBER 2020 REVISED MARCH.
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