LMK5B33414 14-OUT Network Synchronizer Datasheet

LMK5B33414 Key Features

Ultra-low jitter BAW VCO based Ethernet clocks
42-fs typical/ 60-fs maximum RMS jitter at 312.5 MHz
47-fs typical/ 65-fs maximum RMS jitter at 156.25 MHz
3 high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
Programmable DPLL loop bandwidth from 1 mHz to 4 kHz
< 1-ppt DCO frequency adjustment step size
4 differential or single-ended DPLL inputs
1-Hz (1-PPS) to 800-MHz input frequency
Digital holdover and hitless switching
14 differential outputs with programmable HSDS/ LVPECL, LVDS and HSCL output formats

Part Number	Description
LMK5B12204	Ultra-Low Jitter Network Synchronizer Clock
LMK5C33216	Ultra-Low Jitter Clock Synchronizer
LMK00101	Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator
LMK00105	Ultra-Low Jitter LVCMOS Fanout Buffer and Level Translator
LMK00301	3-GHz 10-Output Ultra-Low Additive Jitter Differential Clock Buffer and Level Translator