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SM320C6712D-EP Datasheet Preview

SM320C6712D-EP Datasheet

Digital Signal Processor

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SM320C6712ĆEP, SM320C6712CĆEP, SM320C6712DĆEP
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
D Low-Price/High-Performance Floating-Point
Digital Signal Processors (DSPs):
320C67x(SM320C6712, C6712C, C6712D)
− Eight 32-Bit Instructions/Cycle
− 100-, 167-MHz Clock Rates
− 10-, 6-ns Instruction Cycle Times
− 600, 1000 MFLOPS
D Advanced Very Long Instruction Word
(VLIW) C67xDSP Core
− Eight Highly Independent Functional
Units:
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D Instruction Set Features
− Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
D Device Configuration
− Boot Mode: 8- and 16-Bit ROM Boot
− Endianness: Little Endian (12/12C)
Little Endian, Big Endian (12D)
SGUS055 − SEPTEMBER 2004
D L1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
− 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
D Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
D 16-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− 256M-Byte Total Addressable External
Memory Space
D Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
D Two 32-Bit General-Purpose Timers
D Flexible Phase-Locked-Loop (PLL) Clock
Generator [C6712]
D Flexible Software-Configurable PLL-Based
Clock Generator Module [C6712C/C6712D]
D A Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins [12C/12D]
D IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
D CMOS Technology
− 0.13-µm/6-Level Copper Metal Process
(C6712C/C6712D)
− 0.18-µm/5-Level Metal Process (C6712)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Other trademarks are the property of their respective owners.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but
is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life,
and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
Copyright 2004, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1




etcTI

SM320C6712D-EP Datasheet Preview

SM320C6712D-EP Datasheet

Digital Signal Processor

No Preview Available !

SM320C6712ĆEP, SM320C6712CĆEP, SM320C6712DĆEP
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS
SGUS055 − SEPTEMBER 2004
Table of Contents
GFN BGA package (bottom view) [C6712 only] . . . . . . . . . . 3
GDP BGA package (bottom view) [C6712C/12D only] . . . . 3
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
functional block and CPU (DSP core) diagram . . . . . . . . . . . 7
CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . . 8
memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 11
signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CPU CSR register description . . . . . . . . . . . . . . . . . . . . . . . . 37
cache configuration (CCFG) register description (12D) . . . 39
interrupt sources and interrupt selector [C6712 only] . . . . 40
interrupt sources and interrupt selector [12C/12D only] . . 41
EDMA channel synchronization events [C6712 only] . . . . 42
EDMA module and EDMA selector [12C/12D only] . . . . . . 43
clock PLL [C6712 only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PLL and PLL controller [C6712C/C6712D only] . . . . . . . . . 47
general-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . 54
power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . . 59
EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
EMIF big endian mode correctness [C6712D only] . . . 60
bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
absolute maximum ratings over operating case
temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 61
recommended operating conditions . . . . . . . . . . . . . . . . 62
electrical characteristics over recommended ranges of
supply voltage and operating case temperature . 63
parameter measurement information . . . . . . . . . . . . . . . 64
signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . 65
timing parameters and board routing analysis . . . . . . 65
input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 72
synchronous-burst memory timing . . . . . . . . . . . . . . . . . 75
synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 77
HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
reset timing [C6712] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
reset timing [C6712C/C6712D] . . . . . . . . . . . . . . . . . . . . 87
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 89
multichannel buffered serial port timing . . . . . . . . . . . . . 90
timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
general-purpose input/output (GPIO) port timing
[C6712C/C6712D only] . . . . . . . . . . . . . . . . . . . . . 105
JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
mechanical data [C6712 only] . . . . . . . . . . . . . . . . . . . . 107
mechanical data [C6712C/C6712D only] . . . . . . . . . . . 108
2
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443



Part Number SM320C6712D-EP
Description Digital Signal Processor
Maker etcTI
Total Page 3 Pages
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