Datasheet Summary
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
D High-Impedance State During Power Up and Power Down
D High-Drive Outputs (- 32-mA IOH, 64-mA IOL) D Package Options Include Plastic
Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs description
SN54ABT821, SN74ABT821A 10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS193E
- FEBRUARY 1991
- REVISED MAY...