Overview: SN54ABT8996, SN74ABT8996
10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS489C – AUGUST 1994 – REVISED APRIL 1999 D Members of Texas Instruments Broad
Family of Testability Products Supporting
IEEE Std 1149.1-1990 (JTAG) Test Access
Port (TAP) and Boundary-Scan Architecture
D Extend Scan Access From Board Level to
Higher Levels of System Integration
D Promote Reuse of Lower-Level
(Chip/Board) Tests in System Environment
D Switch-Based Architecture Allows Direct
Connect of Primary TAP to Secondary TAP
D Primary TAP Is Multidrop for Minimal Use of
Backplane Wiring Channels
D Simple Addressing (Shadow) Protocol Is
Received/Acknowledged on Primary TAP
D Shadow Protocols Can Occur in Any of
Test-Logic-Reset, Run-Test/Idle, Pause-DR,
and Pause-IR TAP States to Provide for
Board-to-Board Test and Built-In Self-Test
D 10-Bit Address Space Provides for Up to
1021 User-Specified Board Addresses
D Bypass (BYP) Pin Forces
Primary-to-Secondary Connection Without
Use of Shadow Protocols
D Connect (CON) Pin Provides Indication of
Primary-to-Secondary Connection
D High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Support Backplane Interface at Primary and
High Fanout at Secondary
D Package Options Include Plastic Small-
Outline (DW) and Thin Shrink Small-
Outline (PW) Packages, Ceramic Chip
Carriers (FK), and Ceramic DIPs (JT) SN54ABT8996 . . . JT PACKAGE SN74ABT8996 . . . DW OR PW PACKAGE
(TOP VIEW) A4 1 A3 2 A2 3 A1 4 A0 5 BYP 6 GND 7 PTDO 8 PTCK 9 PTMS 10 PTDI 11 PTRST 12 24 A5 23 A6 22 A7 21 A8 20 A9 19 VCC 18 CON 17 STDI 16 STCK 15 STMS 14 STDO 13 STRST SN54ABT8996 . . .
