SN65DSI83 Overview
The SN65DSI83 DSI to FlatLink bridge device.
SN65DSI83 Key Features
- Implements MIPI® D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
- Single channel DSI receiver configurable for 1, 2, 3, or 4 D-PHY data lanes per channel operating up to 1 Gbps/lane
- Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats
- FlatLink™ output for single-link LVDS
- Supports single channel DSI to single-link LVDS
- LVDS Output Clock Range of 25 MHz to 154 MHz
- LVDS pixel clock may be sourced from free
- 1.8-V main VCC power supply
- Low power features include shutdown mode, reduced LVDS output voltage swing, mon mode, and MIPI ultra-low power state (U
- LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing