SN65DSI83 Datasheet | Texas Instruments

.ti. SN65DSI83 SLLSEC1I - SEPTEMBER 2012 - REVISED OSCNTO6B5EDRS2I08230 SLLSEC1I - SEPTEMBER 2012 - REVISED OCTOBER 2020 SN65DSI83 MIPI® DSI Bridge to Flat Link™ LVDS Single-Channel DSI to Single-Link LVDS Bridge 1 Features - Implements MIPI® D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00 - Single channel DSI receiver configurable for 1, 2, 3, or 4 D-PHY data lanes per channel operating up to 1 Gbps/lane - Supports 18 bpp and 24 bpp DSI video packets with RGB666 and RGB888 formats - Max resolution up to 60 fps WUXGA 1920 × 1200 at 18 bpp and 24 bpp color with reduced blanking. suitable for 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp - Flat Link™ output for single-link LVDS - Supports single channel DSI to single-link LVDS operating mode - LVDS Output Clock Range of 25 MHz to 154 MHz - LVDS pixel clock may be sourced from free- running continuous D-PHY clock or external reference clock (REFCLK) - 1.8-V main VCC power supply - Low power Features include shutdown mode, reduced LVDS output voltage swing, mon mode, and MIPI ultra-low power state (ULPS) support - LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing - ESD rating ±2 k V (HBM) - Packaged in 64-pin 5-mm × 5-mm n FBGA (ZXH) - Temperature range: - 40°C to 85°C 2 Applications - PC & notebooks - Tablets - Connected peripherals & printers 3 Description The SN65DSI83 DSI to Flat Link bridge device Features a single-channel MIPI D-PHY receiver frontend configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a Flat Link-patible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per...