SN65DSI85 Description
The SN65DSI85 DSI to FlatLink bridge.
SN65DSI85 Key Features
- Implements MIPI® D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
- Dual-channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbps
- Supports 18-bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
- MIPI® front-end configurable for single-channel or dual-channel DSI configurations
- FlatLink™ output configurable for single-link or dual-link LVDS
- Supports dual-channel DSI ODD or EVEN and LEFT or RIGHT operating modes
- Supports two single-channel DSI to two single-link LVDS operating mode
- LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link mode
- LVDS pixel clock may be sourced from freerunning continuous D-PHY clock or external reference clock (REFCLK)
- 1.8-V main VCC power supply