SN65DSI84 Description
The SN65DSI84 DSI to FlatLink™ bridge.
SN65DSI84 Key Features
- Implements MIPI® D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
- Single channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbp
- Supports 18 bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
- FlatLink™ output configurable for single-link or dual-link LVDS
- Supports single channel DSI to dual-link LVDS operating mode
- LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link modes
- LVDS pixel clock may be sourced from freerunning continuous D-PHY clock or external reference clock (REFCLK)
- 1.8-V main VCC power supply
- Low power features include shutdown mode
- LVDS channel swap, LVDS PIN order reverse feature for ease of PCB routing