SN65DSI84
Overview
The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a DualLink LVDS, Single-Link LVDS interface with four data lanes per link.
- Implements MIPI® D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
- Single channel DSI receiver configurable for one, two, three, or four D-PHY data lanes per channel operating up to 1 Gbps per lane
- Supports 18 bpp and 24-bpp DSI video packets with RGB666 and RGB888 formats
- Suitable for 60-fps WUXGA 1920 × 1200 resolution at 18-bpp and 24-bpp color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
- FlatLink™ output configurable for single-link or dual-link LVDS
- Supports single channel DSI to dual-link LVDS operating mode
- LVDS output clock range of 25 MHz to 154 MHz in dual-link or single-link modes
- LVDS pixel clock may be sourced from freerunning continuous D-PHY clock or external reference clock (REFCLK)
- 1.8-V main VCC power supply
- Low power features include shutdown mode, reduced LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support
