SN65DSI96 Datasheet | Texas Instruments

FEATURES APPLICATIONS - 234 Embedded Display Port (e DP) 1.4 pliant Supporting 1, 2, or 4 Lanes at 1.62Gbps (RBR), 2.7Gbps (HBR), or 5.4Gbps (HBR2). - Implements MIPI® D-PHY Version 1.1 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00 - Tablet PC, Notebook PC, Netbooks - Mobile Internet Devices LCD e DP TCON - Dual Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1.5Gbps Per Lane - Supports 18 bpp and 24 bpp DSI Video Packets with RGB666 and RGB888 Formats DSI86/96 Dual/Single DSI to e DP - Suitable for 60fps 4K 4096x2304 Resolution at 18bpp Color, and WUXGA 1920x1200 Resolution with 3D Graphics at 60fps (120fps Equivalent) - MIPI® Front-End Configurable for Single Channel or Dual-Channel DSI Configuration DSI- enabled Chipset - Supports Dual Channel DSI ODD/EVEN and DESCRIPTION LEFT/RIGHT Operating Modes - 1.2V Main VCC Power Supply and 1.8V supply for Digital I/Os - Low Power Features Include Panel Refresh and MIPI® Ultra-Low Power State (ULPS) Support - Display Port Lane Polarity and assignment configurable. - Supports 12MHz, 19.2MHz, 26MHz, 27MHz, and The SN65DSI86/96 DSI to embedded Display Port (e DP) bridge features a dual-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1.5Gbps per lane; a maximum input bandwidth of 12Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24bpp RGB888 packets and converts the formatted video data stream to a Display Port with up to four lanes at either 1.62Gbps, 2.16Gbps, 2.43Gbps, 2.7Gbps, 3.24Gbps, 4.32Gbps, or 5.4Gbps. 38.4MHz REFCLK - Adaptive content management and backlight PWM control enabling optimal user viewing experience in both low and bright ambient light environments available in SN65DSI96. - ESD Rating ±4 k V (HBM) The SN65DSI86/96 is well suited for WQXGA at 60 frames per second, as well as 3D Graphics at 4K and True HD (1920x1080) resolutions at an equivalent 120fps with up to 24...