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SN74ACT1073 Datasheet Preview

SN74ACT1073 Datasheet

16-BIT BUS-TERMINATION ARRAY

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D Designed to Ensure Defined Voltage Levels
on Floating Bus Lines in CMOS Systems
D 4.5-V to 5.5-V VCC Operation
D Inputs Accept Voltages to 5.5 V
D Reduces Undershoot and Overshoot
Caused By Line Reflections
D Repetitive Peak Forward
Current . . . IFRM = 100 mA
D Inputs Are TTL-Voltage Compatible
D Low Power Consumption (Like CMOS)
D Center-Pin VCC and GND Configuration
Minimizes High-Speed Switching Noise
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN74ACT1073
16-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002
DW OR NS PACKAGE
(TOP VIEW)
D1 1
D2 2
D3 3
D4 4
GND 5
GND 6
D5 7
D6 8
D7 9
D8 10
20 D16
19 D15
18 D14
17 D13
16 VCC
15 VCC
14 D12
13 D11
12 D10
11 D9
description/ordering information
This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp
the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device
also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path
between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or
pulldown resistors.
The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The
feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state
generated by an active driver before the bus switches to the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C
SOIC − DW
Tube
Tape and reel
SN74ACT1073DW
SN74ACT1073DWR
ACT1073
SOP − NS
Tape and reel SN74ACT1073NSR ACT1073
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2002, Texas Instruments Incorporated
1




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SN74ACT1073 Datasheet Preview

SN74ACT1073 Datasheet

16-BIT BUS-TERMINATION ARRAY

No Preview Available !

SN74ACT1073
16-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002
logic diagram, one of sixteen channels (positive logic)
D1 1
VCC 16
VCC 15
TG
GND 6
GND 5
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Continuous input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Positive-peak input clamp current, IIK (VI > VCC) (tw < 1 μs, duty cycle < 20%) . . . . . . . . . . . . . . . . . . 100 mA
Negative-peak input clamp current, IIK (VI < 0) (tw < 1 μs, duty cycle < 20%) . . . . . . . . . . . . . . . . . . . −100 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input negative-voltage rating may be exceeded if the input clamp-current rating is observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN MAX UNIT
VCC
Supply voltage
4.5 5.5 V
VIH
High-level input voltage
2.5
V
VIL
Low-level input voltage
0.8 V
VI
Input voltage
0 VCC
V
TA
Operating free-air temperature
−40
85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN74ACT1073
Description 16-BIT BUS-TERMINATION ARRAY
Maker etcTI
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SN74ACT1073 Datasheet PDF






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