SN74ACT1073DW Datasheet | Texas Instruments

description /ordering information This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or pulldown resistors. The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state. ORDERING INFORMATION PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING - 40°C to 85°C SOIC - DW Tube Tape and reel SN74ACT1073DW SN74ACT1073DWR ACT1073 - NS Tape and reel SN74ACT1073NSR ACT1073 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at .ti./sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 2002, Texas Instruments Incorporated 1 SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A - MARCH 1992 - REVISED NOVEMBER 2002 logic diagram, one of sixteen channels (positive logic) D1 1 VCC 16 VCC 15 TG GND 6 GND 5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply...