Texas Instruments SN74ACT1073
The SN74ACT1073 prevents bus lines from floating without using pullup or pulldown resistors. The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state generated by an active driver before the bus switches to the high-impedance state.D Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Reduces Undershoot and Overshoot Caused By Line Reflections D Repetitive Peak Forward Current . . . IFRM = 100 mA D Inputs Are TTL-Voltage Compatible D Low Power Consumption (Like CMOS) D Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 DW OR NS PACKAGE (TOP VIEW) D1 1 D2 2 D3 3 D4 4 GND 5 GND 6 D5 7 D6 8 D7 9 D8 10 20 D16 19 D15 18 D14 17 D13 16 VCC 15 VCC 14 D12 13 D11 12 D10 11 D9 description/ordering information This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity.