D Designed to Ensure Defined Voltage Levels
on Floating Bus Lines in CMOS Systems
D 4.5-V to 5.5-V VCC Operation
D Inputs Accept Voltages to 5.5 V
D Reduces Undershoot and Overshoot
Caused By Line Reflections
D Repetitive Peak Forward
Current . . . IFRM = 100 mA
D Inputs Are TTL-Voltage Compatible
D Low Power Consumption (Like CMOS)
D Center-Pin VCC and GND Configuration
Minimizes High-Speed Switching Noise
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
16-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002
DW OR NS PACKAGE
This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp
the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device
also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path
between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or
The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The
feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state
generated by an active driver before the bus switches to the high-impedance state.
−40°C to 85°C
SOIC − DW
Tape and reel
SOP − NS
Tape and reel SN74ACT1073NSR ACT1073
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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