SN74ACT1073DW Datasheet | Texas Instruments

D Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Reduces Undershoot and Overshoot Caused By Line Reflections D Repetitive Peak Forward Current . . . IFRM = 100 mA D Inputs Are TTL-Voltage patible D Low Power Consumption (Like CMOS) D Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise D ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A - MARCH 1992 - REVISED NOVEMBER 2002 DW OR NS PACKAGE (TOP VIEW) D1 1 D2 2 D3 3 D4 4 GND 5 GND 6 D5 7 D6 8 D7 9...