SN74AUP1G00 Description
This single 2-input positive-NAND gate performs the Boolean function Y = A × B or Y = A + B in positive logic. Logic Diagram (Positive Logic) A Y B 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. SN74AUP1G00 SCES604J SEPTEMBER 2004 REVISED DECEMBER 2016 .ti.
SN74AUP1G00 Key Features
- 1 ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
- Available in the Ultra Small 0.64 mm2 Package
- Low Static-Power Consumption (ICC = 0.9 µA Max)
- Low Dynamic-Power Consumption (Cpd = 4 pF Typical at 3.3 V)
- Low Input Capacitance (Ci = 1.5 pF Typical)
- Low Noise Overshoot and Undershoot
- Ioff Supports Live Insertion, Partial-Power-Down
- Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input (Vhys = 250 mV Typical at 3.3
SN74AUP1G00 Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II