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SN74AUP1G32 - Low-Power Single 2-Input Positive-OR Gate

Description

This single 2-input positive-OR gate performs the Boolean function Y = A

B or Y = A +B in positive logic.

BODY SIZE (NOM) 1.60 mm × 1.20 mm 1.45 mm × 1.00 mm 0.80 mm × 0.80 mm 1.19 mm × 0.

Features

  • Available in the ultra-small 0.64 mm2 package (DPW) with 0.5-mm pitch.
  • Low static-power consumption (ICC = 0.9 µA Max).
  • Low dynamic-power consumption (Cpd = 4.3 pF Typ at 3.3 V).
  • Low input capacitance (CI = 1.5 pF Typ).
  • Low noise.
  • overshoot and undershoot.

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Full PDF Text Transcription

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www.ti.com SN74AUP1G32 SCES580K – JUNE 2004 – RSENV7IS4EADUMPAY1G203220 SCES580K – JUNE 2004 – REVISED MAY 2020 SN74AUP1G32 Low-Power Single 2-Input Positive-OR Gate 1 Features • Available in the ultra-small 0.64 mm2 package (DPW) with 0.5-mm pitch • Low static-power consumption (ICC = 0.9 µA Max) • Low dynamic-power consumption (Cpd = 4.3 pF Typ at 3.3 V) • Low input capacitance (CI = 1.5 pF Typ) • Low noise – overshoot and undershoot <10% of VCC • Ioff Supports live insertion, partial-power-down mode, and back drive protection • Input hysteresis allows slow input transition and better switching noise immunity at the input (Vhys = 250 mV typ at 3.3 V) • Wide operating VCC range of 0.8 V to 3.6 V • Optimized for 3.3-V operation • 3.
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