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SN74LVC112A - Dual Negative-Edge-Triggered J-K Flip-Flop

Product Overview

Texas Instruments

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SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop by Texas Instruments - Datasheet Preview — Datasheet preview – SN74LVC112A

Datasheet Details

Part number	SN74LVC112A
Manufacturer	Texas Instruments
File Size	1.05 MB
Description	Dual Negative-Edge-Triggered J-K Flip-Flop
Datasheet	SN74LVC112A Datasheet
Additional preview pages of the SN74LVC112A datasheet.

Product details

Description

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.

Features

1 Operates From 1.65 V to 3.6 V.
Inputs Accept Voltages to 5.5 V.
Max tpd of 4.8 ns at 3.3 V.
Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C.
Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C.
Latch-Up Performance Exceeds 250 mA Per JESD 17.
ESD Protection Exceeds JESD 22.
3000-V Human-Body Model.
200-V Machine Model.
1500-V Charged-Device Model 2.

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Published: Nov 14, 2020 |