TMS320C6203B Description
− Six ALUs (32-/40-Bit) − Two 16-Bit Multipliers (32-Bit Result) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set.
TMS320C6203B Key Features
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
- 3M-Bit Internal Program/Cache (96K 32-Bit Instructions)
- 4M-Bit Dual-Access Internal Data (512K Bytes)
- Organized as Two 256K-Byte Blocks for Improved Concurrency
- Glueless Interface to Synchronous Memories: SDRAM or SBSRAM