74AHCT74D, 74AHC74 Datasheet - nexperia

74AHCT74D Dual D-type flip-flop

The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP).

74AHCT74D Features

* Balanced propagation delays

* All inputs have Schmitt-trigger actions

* Inputs accept voltages higher than VCC

* Input levels:

* For 74AHC74: CMOS level

* For 74AHCT74: TTL level

* ESD protection:

* HBM EIA/JESD22-A114E exceeds 2000 V

74AHC74-nexperia.pdf