74AUP1G175 flip-flop equivalent, low-power d-type flip-flop.
* Wide supply voltage range from 0.8 V to 3.6 V
* High noise immunity
* CMOS low power dissipation
* Complies with JEDEC standards:
* JESD8-12 (0.8 V .
using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the dev.
The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be.
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