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74AUP1G175-Q100 - Low-power D-type flip-flop

Description

The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • Wide supply voltage range from 0.8 V to 3.6 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3 V).
  • JESD8-11 (0.9 V to 1.65 V).
  • JESD8-7 (1.2 V to 1.95 V).
  • JESD8-5 (1.8 V to 2.7 V).
  • JESD8C (2.7 V to 3.6 V).

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Datasheet preview – 74AUP1G175-Q100

Datasheet Details

Part number 74AUP1G175-Q100
Manufacturer nexperia
File Size 262.20 KB
Description Low-power D-type flip-flop
Datasheet download datasheet 74AUP1G175-Q100 Datasheet
Additional preview pages of the 74AUP1G175-Q100 datasheet.

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Full PDF Text Transcription

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74AUP1G175-Q100 Low-power D-type flip-flop with reset; positive-edge trigger Rev. 4 — 18 January 2022 Product data sheet 1. General description The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
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