74AUP1G175 Datasheet - NXP

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74AUP1G175 Low Power D-Type Flip-Flop

www.DataSheet4U.com 74AUP1G175 Low-power D-type ﬂip-ﬂop with reset; positive-edge trigger Rev.01 * 15 November 2006 Product data sheet 1.G.
The 74AUP1G175 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

74AUP1G175_PhilipsSemiconductors.pdf

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Datasheet Details

Part number:

74AUP1G175

Manufacturer:

NXP ↗

File Size:

146.94 KB

Description:

Low Power D-Type Flip-Flop

Features

* s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-D Class 3A exceeds 500

Applications

* using IOFF. The IOFF circuitry disables the output, preventing the damaging backﬂow current through the device when it is powered down. The 74AUP1G175 is a single positive-edge triggered D-type ﬂip-ﬂop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master

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74AUP1G175 Low Power D-Type Flip-Flop NXP

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