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74AUP1G132 - Low-power 2-input NAND Schmitt trigger

Datasheet Summary

Description

The 74AUP1G132 is a single 2-input NAND gate with Schmitt-trigger inputs.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

Features

  • Wide supply voltage range from 0.8 V to 3.6 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Overvoltage tolerant inputs to 3.6 V.
  • Low static power consumption; ICC = 0.9 μA (maximum).
  • Latch-up performance exceeds 100 mA per JESD 78 Class II.
  • Low noise overshoot and undershoot < 10 % of VCC.
  • IOFF circuitry provides partial Power-down mode operation.
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3.

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Datasheet Details

Part number 74AUP1G132
Manufacturer nexperia
File Size 281.43 KB
Description Low-power 2-input NAND Schmitt trigger
Datasheet download datasheet 74AUP1G132 Datasheet
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Full PDF Text Transcription

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74AUP1G132 Low-power 2-input NAND Schmitt trigger Rev. 8 — 14 January 2022 Product data sheet 1. General description The 74AUP1G132 is a single 2-input NAND gate with Schmitt-trigger inputs. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 0.8 V to 3.6 V • CMOS low power dissipation • High noise immunity • Overvoltage tolerant inputs to 3.
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