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74AUP1G17 - SINGLE SCHMITT-TRIGGER BUFFER

General Description

The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.

The AUP1G17 is a single 1-input Schmitt-trigger buffer gate with a push-pull output designed for operation over a power supply range of 0.8V to 3.6V.

Key Features

  • Advanced Ultra Low Power (AUP) CMOS.
  • Supply Voltage Range from 0.8V to 3.6V.
  • ±4mA Output Drive at 3.0V.
  • Low Static power consumption.
  • Icc < 0.9µA.
  • Low Dynamic Power Consumption.
  • CPD = 6pF (Typical at 3.6).
  • Schmitt Trigger Action at All Inputs Make the Circuit Tolerant for Slower Input Rise and Fall Time. The hysteresis is typically 250mV at Vcc = 3.0V.
  • IOFF Supports Partial-Power-Down Mode Operation.
  • ESD Protection Exceeds JESD 22.
  • 2000-V H.

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74AUP1G17 SINGLE SCHMITT-TRIGGER BUFFER Description The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. Pin Assignments The AUP1G17 is a single 1-input Schmitt-trigger buffer gate with a push-pull output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. The gate performs the positive Boolean function: YA Future Product Features  Advanced Ultra Low Power (AUP) CMOS  Supply Voltage Range from 0.8V to 3.6V  ±4mA Output Drive at 3.0V  Low Static power consumption  Icc < 0.