74AUP1G17 Description
The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. Pin Assignments The AUP1G17 is a single 1-input Schmitt-trigger buffer gate with a push-pull output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF.
74AUP1G17 Key Features
- Advanced Ultra Low Power (AUP) CMOS
- Supply Voltage Range from 0.8V to 3.6V
- ±4mA Output Drive at 3.0V
- Low Static power consumption
- Icc < 0.9µA
- Low Dynamic Power Consumption
- CPD = 6pF (Typical at 3.6)
- IOFF Supports Partial-Power-Down Mode Operation
- ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)