74AUP1G3208
74AUP1G3208 is Low-power 3-input OR-AND gate manufactured by Nexperia.
Low-power 3-input OR-AND gate
Rev. 10
- 9 May 2023
Product data sheet
1. General description
The 74AUP1G3208 is a single 3-input OR-AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
2. Features and benefits
- Wide supply voltage range from 0.8 V to 3.6 V
- High noise immunity
- plies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- ESD protection:
- HBM JESD22-A114F Class 3A exceeds 5000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101E exceeds 1000 V
- Low static power consumption; ICC = 0.9 μA (maximum)
- Latch-up performance exceeds 100 m A per JESD 78 Class II
- Overvoltage tolerant inputs to 3.6 V
- Low noise overshoot and undershoot < 10 % of VCC
- IOFF circuitry provides partial Power-down mode operation
- Multiple package options
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
Low-power 3-input OR-AND gate
3. Ordering information
Table 1. Ordering...
