74AUP1G74 - Low-power D-type flip-flop

Product Overview

nexperia

Datasheet Details

Part number	74AUP1G74
Manufacturer	nexperia
File Size	344.92 KB
Description	Low-power D-type flip-flop
Datasheet	74AUP1G74 Datasheet
Additional preview pages of the 74AUP1G74 datasheet.

Product details

Description

The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs.

Features

Wide supply voltage range from 0.8 V to 3.6 V.
CMOS low power dissipation.
High noise immunity.
Overvoltage tolerant inputs to 3.6 V.
Low static power consumption; ICC = 0.9 μA (maximum).
Latch-up performance exceeds 100 mA per JESD 78 Class II.
Low noise overshoot and undershoot < 10 % of VCC.
IOFF circuitry provides partial Power-down mode operation.
Complies with JEDEC standards:.
JESD8-12 (0.8 V to 1.3.

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Published: Jul 23, 2019 |