900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






nexperia

74HC10-Q100 Datasheet Preview

74HC10-Q100 Datasheet

Triple 3-input NAND gate

No Preview Available !

74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
Rev. 1 — 21 February 2013
Product data sheet
1. General description
The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Complies with JEDEC standard JESD7A
Input levels:
For 74HC10-Q100: CMOS level
For 74HCT10-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC10D-Q100
40 C to +125 C SO14
74HCT10D-Q100
74HC10PW-Q100
40 C to +125 C TSSOP14
74HCT10PW-Q100
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
Version
SOT108-1
SOT402-1




nexperia

74HC10-Q100 Datasheet Preview

74HC10-Q100 Datasheet

Triple 3-input NAND gate

No Preview Available !

Nexperia
4. Functional diagram
74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
1 1A
2 1B
13 1C
3 2A
4 2B
5 2C
9 3A
10 3B
11 3C
1Y 12
2Y 6
3Y 8
mna757
Fig 1. Logic symbol
1
2 & 12
13
3
4 &6
5
9
10 & 8
11
mna759
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
BY
C
mna758
Fig 3. Logic diagram for one gate
+&4
+&74
$ 
% 
$ 
% 
& 
< 
*1' 
 9&&
 &
 <
 &
 %
 $
 <
DDD
Fig 4. Pin configuration SO14
+&4
+&74
$ 
% 
$ 
% 
& 
< 
*1' 
 9&&
 &
 <
 &
 %
 $
 <
DDD
Fig 5. Pin configuration TSSOP14
5.2 Pin description
Table 2. Pin description
Symbol
Pin
1A, 2A, 3A
1, 3, 9
1B, 2B, 3B
2, 4, 10
GND
7
1C, 2C, 3C
13, 5, 11
1Y, 2Y, 3Y
12, 6, 8
VCC 14
Description
data input
data input
ground (0 V)
data input
data output
supply voltage
74HC_HCT10_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 February 2013
© Nexperia B.V. 2017. All rights reserved
2 of 13


Part Number 74HC10-Q100
Description Triple 3-input NAND gate
Maker nexperia
Total Page 13 Pages
PDF Download

74HC10-Q100 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 74HC10-Q100 Triple 3-input NAND gate
nexperia





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy