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74HC107-Q100 Datasheet Preview

74HC107-Q100 Datasheet

Dual JK flip-flop

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74HC107-Q100; 74HCT107-Q100
Dual JK flip-flop with reset; negative-edge trigger
Rev. 2 — 26 January 2015
Product data sheet
1. General description
The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop
featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q
and Q outputs. The reset is an asynchronous active LOW input and operates
independently of the clock input. The J and K inputs control the state changes of the
flip-flops as described in the mode select function table. The J and K inputs must be stable
one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs
include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC107-Q100: CMOS level
For 74HCT107-Q100: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC107D-Q100
40 C to +125 C
74HCT107D-Q100
74HC107PW-Q100 40 C to +125 C
Name
SO14
Description
Version
plastic small outline package; 14 leads; body width SOT108-1
3.9 mm
TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm




nexperia

74HC107-Q100 Datasheet Preview

74HC107-Q100 Datasheet

Dual JK flip-flop

No Preview Available !

Nexperia
4. Functional diagram
74HC107-Q100; 74HCT107-Q100
Dual JK flip-flop with reset; negative-edge trigger
 - -
 -
 &3
))
&3
 &3
4 4
4




.
.
.
4 4 
4 
5
5 5
 
DDD
Fig 1. Logic symbol
 -
 &
 .
 5
 -
 &
 .
 5
Fig 2. IEC logic symbol




DDD
&
.
-
&
5
&3 &
&
Fig 3. Logic diagram (one flip-flop)
&
&
&&
&&
DDE
4
4
74HC_HCT107_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 January 2015
© Nexperia B.V. 2017. All rights reserved
2 of 17


Part Number 74HC107-Q100
Description Dual JK flip-flop
Maker nexperia
Total Page 17 Pages
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