ADS4616A4A - Synchronous DRAM

This page provides the datasheet information for the ADS4616A4A, a member of the ADS Synchronous DRAM family.

Datasheet Summary

Description

The ADS4616A4A are two-bank Synchronous DRAMs organized as 524,288 words x 16 bits x 2 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Features

Single 3.3V +/- 0.3V power supply.
MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,4,8, & full page) -Burst Type (sequential & Interleave).
2 banks operation.
All inputs are sampled at the positive edge of the system clock.
Burst Read single write operation.
Auto & Self refresh.
4096 refresh cycle.
DQM for masking.
Package:50-pins 400 mil TSOP-Type II Ordering Information. Part No. ADS4616A4A-5.

A-Data Technology

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Datasheet Details

Part number	ADS4616A4A
Manufacturer	A-Data Technology
File Size	203.24 KB
Description	Synchronous DRAM
Datasheet	ADS4616A4A Datasheet
Additional preview pages of the ADS4616A4A datasheet.

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Full PDF Text Transcription

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A-Data Synchronous DRAM ADS4616A4A 512K x 16 Bit x 2 Banks General Description The ADS4616A4A are two-bank Synchronous DRAMs organized as 524,288 words x 16 bits x 2 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features •Single 3.3V +/- 0.

Published: Mar 23, 2005 |