AM79C850 Datasheet - AMD

AM79C850 - SUPERNET 3

. The SUPERNET 3 is backward compatible to the SUPERNET 2 Tag Mode of operation in which the SUPERNET 3 buffer memory interface logic maintains the buffer memory as multiple FIFOs. The SUPERNET 3 provides DMA channels, arbitrates access to the network buffer memory, and controls the data path betwee.

PRELIMINARY Am79C850 SUPERNET® 3 DISTINCTIVE CHARACTERISTICS s Compliant with the ANSI X3T9.5/ISO 9314 Advanced Micro Devices s ANSI-compliant TP-PMD Stream Cipher specification 100 Mbps data rate Timed token-passing protocol www.DataSheet4U.com Ring topology s Complete memory management Supports 256K bytes of local frame buffer memory Supports buffer memory bandwidths of 200 Mbps and 400 Mbps Tag-Mode: minimum latency/highest perfo.

AM79C850 Features

* Built in Self Test (BIST) in Address Filter, Physical Layer Controller with Scrambler s Hardware Physical Connection Management support s Low power consumption

* reduction of more than 25% from SUPERNET 2 solution FUNCTIONAL OVERVIEW SUPERNET 3 is a 208-pin CMOS integration of FDD

AM79C850_AMD.pdf