A67L8336 Datasheet - AMIC Technology

A67L8336 512K X 18- 256K X 36 LVTTL / Pipelined ZeBL SRAM

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L9318, A67L8336 SRAMs integrate a 512K X 18, 256K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 10.

A67L8336 Features

* Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled a

A67L8336 Datasheet (289.88 KB)