* Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled a
A67L8336 Datasheet (289.88 KB)
A67L8336
AMIC Technology
289.88 KB
512k x 18- 256k x 36 lvttl / pipelined zebl sram.
www.DataSheet4U.com A67L9318/A67L8336 Preliminary Document Title 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 512.
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