* Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered addr
A67L93181 Datasheet (280.34 KB)
A67L93181
AMIC Technology
280.34 KB
512k x 18- 256k x 36 lvttl / flow-through zebl sram.
www.DataSheet4U.com A67L93181/A67L83361 Preliminary Document Title 512K X 18, 256K X 36 LVTTL, Flow-through ZeBLTM SRAM Revision History Rev. No. 0.0.
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