* Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled a
A67L9336 Datasheet (252.34 KB)
A67L9336
AMIC Technology
252.34 KB
(a67l0618 / a67l9336) pipelined zebl sram.
A67L0618/A67L9336 Preliminary Document Title 1M X 18, 512K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 1M X 18, 512K X 36 LVTTL, .
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