Description
Table 1:
Name Pin Description I/O Active Description
Buses U1D[0..15] U2D[0..15] ΜD[0..15] ΜC[0..7] Error Flags CERR NCERR 26 25 O O Low Low Correctable Error Uncorrectable Error 53,49..47,45..42,40..37,35..33,28 23..20,18..15,13..10,8..5 59..62,64..67,69..72,74..77 83..86,88..91 I/O
I/O
I/O
I/O
High High High High User 1 Data Bus User 2 Data Bus Memory Data Bus Memory Check
bit Bus
General Control Signals CORRECT SYNCHK N22 TRANS 98 97 27 96 I
I
I
I
Features
- D D D D D D D D
Very Low Power CMOS 16.
- Bit operation with 6 or 8 Check Bits Fast Error Detection : 31 ns (max. ) Fast Error Correction : 32 ns (max. ) Corrects all Single.
- Bit Errors Detects all Double.
- Bit Errors Detects some Multi.
- Bit Errors Detects Chip Errors (x1, x4 & x8 RAM Format)
D D D D D D D
Correctable and Uncorrectable Error Flags Two User Data Buses User to User Transfer and Listening operation High Drive Capability on Buses :.
- 12.8 mA TTL Comp.
29C516E_ATMELCorporation.pdf
