Datasheet Specifications
- Part number
- AS7C33256PFD18B
- Manufacturer
- Alliance Semiconductor Corporation
- File Size
- 582.27 KB
- Datasheet
- AS7C33256PFD18B_AllianceSemiconductorCorporation.pdf
- Description
- 3.3V 256K x 18 pipeline burst synchronous SRAM
Description
February 2005 ® AS7C33256PFD18B 3.3V 256K × 18 pipeline burst synchronous SRAM .
Features
* Organization: 262,144 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous register-to-register operation Double-cycle deselect AsynApplications
* Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate iAS7C33256PFD18B Distributors
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