Description
March 2001 ® AS7C33256PFS16A AS7C33256PFS18A 3.3V 256K × 16/18 pipeline burst synchronous SRAM .
The AS7C33256PFS16A and AS7C33256PFS18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) devices organized as 262,144 w.
Features
* Organization: 262,144 words × 16 or 18 bits
* Fast clock speeds to 166 MHz in LVTTL/LVCMOS
* Fast clock to data access: 3.5/3.8/4.0/5.0 ns
* Fast OE access time: 3.5/3.8/4.0/5.0 ns
* Fully synchronous register-to-register operation
* “Flow-through” m
Applications
* Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/ 18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting BWE and the appropria
